A 90 nm area and power efficient Carry Select Adder using 2–1 multiplexer based Excess-1 block

Abstract This paper proposes a novel architecture of excess-1 adder-based Carry Select Adder (M2CSA) using single leaf cell i.e., 2–1 Multiplexer. M2CSA is designed new type Excess-1 block. The block in distinct way multiplexers. architectures the proposed carry select adder and its internal blocks are completely when compared to existing adders. 4-, 8-, 16-, 32-, 64-bit M2CSAs use multiplexer only. complex gates such as XOR eliminated which exist Adders (CaSeAs). A that utilises one kind 2-1 Mux clearly decomposed retain outstanding regularity. In previous designs, ripple substituted with half adders by limiting propagation particular degree. By avoiding over blocks, particularly 32- adders, performance initially increased. For CaSeAs, area primary significance; for M2CSAs, it also diminished preserving Verilog HDL utilised design current CaSeAs. Using Cadence NCLaunch, all designs functionally tested. At 90nm technology node, generated executed Genus Innovus tools, respectively. As comparison prior final ASIC on average 17% less terms space. result analysis show performs 20% 19% faster than SQCSC power dissipation, respectively.. 64- bit exhibits PDP (Power-Delay Product) ranging from 25%–30% concerning SQCSCs. Similarly, EDP (Energy- Delay values calculated. improvement 41, 38, 42, 43, 45 percentages Therefore, outperform 38%–45%.